1. Field of the Invention
The present invention relates generally, to an SRAM cell arrangement having a plurality of memory cells, and more specifically to an SRAM cell arrangement wherein each of its memory cells respectively includes six vertical MOS transistors such that various contacts contact a plurality of parts of the transistor simultaneously.
2. Description of the Related Art
An SRAM cell arrangement is a memory cell arrangement with random access to stored information. In contrast to a DRAM cell arrangement wherein the information must be refreshed at regular time intervals, the information is statically stored in an SRAM cell arrangement.
What are referred to as 6T memory cells are being increasingly utilized in SRAM cell arrangements. A 6T memory cell includes four MOS transistors interconnected as a flipflop and two selection transistors. The flipflop is one of the two stable conditions. The condition of the flipflop represents a logical quantity, 0 or 1. By driving the selection transistors via a word line, the condition can be determined via two bit lines. Thus, the information can be read out and the condition can be modified and, thus, new information can be stored.
Since the memory density is increasing from memory generation to memory generation, the required area of the 6 T memory cell must be reduced from generation to generation. Semiconductor International (November 1996) pages 19 and 20, presents a 6T memory cell that can be manufactured with an area of 55 F.sup.2, whereby F is the minimum structural size that can be manufactured in the respective technology. Self-aligned contacts (i.e., contacts without utilization of aligning masks), are produced and local connections (i.e., connections that lie within the cell), are utilized.
The present invention is based on the problem of specifying an SRAM cell arrangement that includes 6 T memory cells as memory cells and can be manufactured with especially high packing density. Further, a manufacturing method for such an SRAM cell arrangement should be specified.